Non-uniform sampling has proven through different works, to be a better scheme than the uniform sampling to sample low activity signals. With such signals, it generates fewer samples, which means less data to process and lower power consumption. In addition, it is well-known that asynchronous logic is a low power technology. This paper deals with the coupling between a non-uniform sampling scheme and an asynchronous design in order to implement a digital Filter. This paper presents the first design of a micropipeline asynchronous FIR filter architecture coupled to a non-uniform sampling scheme. The implementation has been done on an Altera FPGA board.
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